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| NJU8715 PRELIMINARY Switching Driver with Regulator for Class-D Headphone Amplifier GENERAL DESCRIPTION The NJU8715 is a switching driver with regulator for class-D headphone amplifier. It incorporates an optimum regulator for the driver of headphone amplifier, class-D line amplifier and a beep amplifier. The NJU8715 converts 1bit digital signal of the PWM or the PDM to an analog signal output through a simple external LC low-pass filter. The NJU8715 provides a completed digital system and high power-efficiency with class-D operation. Therefore, it is suitable for portable audio applications. PACKAGE OUTLINE NJU8715KN1 FEATURES 2-channel 1bit Audio Signal Input Headphone Output Built-in Class D Line Amplifier Built-in Regulator for Driver Beep Function Logic Operating Voltage 1.9 to 2.6V (VDD) Regulator Operating Voltage 4.0 to 5.75V (VG) 1.9 to 4.0V (VREG) C-MOS Technology Package Outline QFN28 PIN CONFIGURATION 28 1 MODEB BEEPIN DIN2 DIN1 OBEEP1 VSS OUT1 CL CH VG NC OBEEP2 VSS OUT2 VDDO1 VREGO VREG VCONT VREF CFB VDDO2 VCONT ENVG ENREG EN2 EN1 VDD MCK VSS VDD VSS DIN1 Charge Pump Level Shifter Level Shifter Pre Driver Regulator VDDO1 HP Amp VREGO BLOCK DIAGRAM VREG CH VG CL VREF CFB OUT1 Pre Driver LINE Amp VSS VDDO2 MCK Level Shifter Pre Driver HP Amp OUT2 DIN2 Level Shifter Pre Driver LINE Amp VSS OBEEP1 OBEEP2 BEEPIN Level Shifter BEEP Amp BEEP Amp Control Logic Ver.2005-03-09 MODEB ENREG EN1 EN2 ENVG -1- NJU8715 TERMINAL DESCRIPTION No. 1 2 3 4 5 6, 16, 22 7 8 9 10 11 12 13 14 15 17 18 19 20 21 23 24 25 26 27 28 SYMBOL MODE B BEEPIN DIN2 DIN1 OBEEP1 VSS OUT1 VDDO1 VREGO VREG VCONT VREF CFB VDDO2 OUT2 OBEEP2 NC VG CH CL MCK VDD EN1 EN2 ENREG ENVG I/O I I I I O O O I I O I O O I I I I I Function BEEP Output Level Control Terminal H: -39dBm, L: -48dBm The load of 16 (Note.1) BEEP Signal Input Terminal Audio Signal Input Terminal 2 Audio Signal Input Terminal 1 BEEP Output Terminal 1 Power GND: VSS=0V (Note.2) Output Terminal 1 This terminal outputs DIN1 terminal input data. Driving Power Supply 1 Regulator Output Terminal Regulator Input Terminal Regulator Output Voltage Control Terminal Reference Voltage Output Terminal Regulator Output Voltage Sense Terminal Driving Power Supply 2 Output Terminal 2 This terminal outputs DIN2 terminal input data. BEEP Output Terminal 2 Non connection Pre-driver Power supply + Capacitor Connection Terminal for the charge pump - Capacitor Connection Terminal for the charge pump Master Clock Input Terminal The condition of the data input terminal is latched on the rising edge of this signal. Operation Power Supply HP/LINE/BEEP Mode Control Terminal 1 (with pull-down resistor) HP/LINE/BEEP Mode Control Terminal 2 (with pull-down resistor) Regulator Enable Terminal (with pull-down resistor) H : ON, L : OFF Charging pump Enable Terminal (with pull-down resistor) H : ON, L : OFF Note.1) 0dBm0.775Vrms Note.2) VSS(Terminal No.6,16,22) should be connected at the nearest point to the IC. INPUT TERMINAL STRUCTURE MCK, DIN1, DIN2, BEEPIN, MODEB Terminal VDD EN1, EN2, ENREG, ENVG Terminal VDD Input Terminal VSS Input Terminal VSS -2-2- Ver.2005-03-09 NJU8715 NJU3555 FUNCTIONAL DESCRIPTION (1) Power Supply VDD : Power supply for input circuit and control logic. Keep the input logic level less than VDD. VG : Power supply for pre-driver which drives the transistor gates of output drivers. When ENVG=H, charge pump generates double the voltage of VDD, which is supplied to VG terminal through the inside. When ENVG=L, charge pump is halted, and VG terminal accepts the external power supply. VREG : Power supply for built-in regulator. Apply the required voltage with additional dropout voltage of regulator. By connecting VREGO (regulator output) to VDDO1, VDDO2 (Driver power supply), the power is provided to the drivers. Furthermore, the regulator output should be supplied to VDDO1 and VDDO2 by connecting de-coupling capacitor to get highly smoothed power supply. (2) Regulator Output Voltage Control Terminal (VCONT) VCONT is the control terminal for regulator output voltage. As VREG output voltage is variable from 0V by external DC voltage, driver output level can be used as sound volume. The regulator is halted at "L" level, and works at "H" level. The charge pump is halted at "L" level, and works at "H" level. Each mode can be selected by a combination setting of EN1 and EN2. The following table shows each output condition of each mode. Mode Standby Mode LINE Mode HP Mode BEEP Mode Input EN1 EN2 L L L H H L H H Output LINE Amp. HiZ Active HiZ HiZ (3) Regulator Enable Signal (ENREG) (4) Charging pump Enable Signal (ENVG) (5) HP/LINE/BEEP Mode Control Terminal (EN1 / EN2) HP Amp. HiZ HiZ Active HiZ BEEP Amp. HiZ HiZ HiZ Active (6) BEEP Signal Input (BEEPIN) (7) BEEP Signal Output (OBEEP1 / OBEEP2) (8) Master Clock (MCK) Master clock (MCK) synchronizes the audio signal inputs(DIN1, DIN2). The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are latched on the rising edge of MCK. During the standby condition, MCK requires "L" level to avoid unnecessary power consumption. In addition, MCK requires jitter-free or fewer jitter because the jitter could lead to poor S/N ratio. (9) Signal output (OUT1 / OUT2) OUT1 and OUT2 terminals keep the Hi-z condition if output voltage of VREGO is lower than detection voltage. Output signals are appeared as PWM signals through the use of VDDO1 and VDDO2 in the OUT1 and OUT2 terminals If the output voltage is over than detection voltage. Output signals will be converted to analog signals via 2nd-order or higher LC filter. BEEP signal is output in a square wave. Ver.2005-03-09 -3- NJU8715 POWER ON/DOWN SEQUENCE The pop-noise can be effectively suppressed with the following sequence when power ON and DOWN. (1) Power ON / Power DOWN Sequence (ENVG=H: Using internal VG) < Power On sequence > 1) Input the MCK after the start-up of VDD. After of 100ms delay or more from MCK input, set ENVG at "H" level. 2) Set ENSEG at "H" level after 5ms delay or more.(at 0.1F for the charge pump and 1F for the smoothing capacitor) 3) After setting ENREG at "H" level, input audio signals(DIN1, DIN2). 4) Set EN1 at "H" level and EN2 at "L" level after audio signal input. The audio signal input must be "Sound-less data" until VCONT reaches a steady state. 5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target VCONT voltage is short, it may cause a pop-noise. < Power Down sequence > The sequence must be executed in inverse order of the power ON sequence. VDD, VREG ENVG VG ENREG VCONT 100ms or more 100ms or more EN1 EN2 MCK DIN1, DIN2 Undefined Data* Sound-less Data Audio Data Sound-les Data Undefined Data* High impedance OUT1, OUT2 High impedance Audio signal output * : Do not set DIN1 and DIN2 at "H" level before the start-up of VDD. -4-4- Ver.2005-03-09 NJU8715 NJU3555 (2)Power ON / Power DOWN Sequence(ENVG=L, VG: Externally applied) < Power ON sequence > 1) Input the MCK after the start-up of VDD. Apply VG after the start-up VDD.(As shown in the following sequence, VG increases to VDD through a internal protection diode after VDD is turned on.) 2) Set ENREG at "H" level after the start-up of VG. 3) After setting ENREG at "H" level, input audio signals(DIN1, DIN2). 4) Set EN1 at "H" level and EN2 at "L" level after audio signal input. The audio signal input must be "Sound-less data" until VCONT reaches a steady state. 5) VCONT should be applied gradually to the target voltage. If the rising time of the application to the target VCONT voltage is short, it may cause a pop-noise. < Power DOWN sequence > The sequence must be executed in inverse order of the power ON sequence. VDD, VREG ENVG VG ENREG VCONT 100ms or more 100ms or more EN1 EN2 MCK DIN1, DIN2 Undefined Data* Sound-less Data Audio data Sound-less Data Undefined Data* High impedance OUT1, OUT2 High impedance Audio signal output * : Do not set DIN1 and DIN2 at "H" level before the start-up of VDD. Ver.2005-03-09 -5- NJU8715 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage SYMBOL VDD VREG VG Input Voltage Operating Temperature Storage Temperature Power Dissipation Vin Ta Tstg PD RATING -0.3 ~ +2.75 -0.3 ~ +5.5 VDD ~ +6.0 -0.3 ~ VDD+0.3 -20 ~ +85 -40 ~ +125 640 (Ta=25C) UNIT V V V V C C mW Note.3) The relations of VDDO1,VDDO2 Ver.2005-03-09 NJU8715 NJU3555 ELECTRICAL CHARACTERISTICS (1) DC CHARACTERISTICS (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) CONDITIONS MIN TYP MAX UNIT 1.9 VG: Externally applied OUT1, 2=VDDO1, 2-0.1V OUT1, 2=0.1V OUT1, 2=VDDO1, 2-0.1V VDDO1, 2=2.75V OUT1, 2=0.1V VDDO1, 2=2.75V MODEB=L MODEB=H Standby Mode Stopping MCK,DIN1,DIN2,BEEPIN ENREG=L Using internal VG HP Mode No-load operating, MCK=256fs DIN1,DIN2=16fs, ENREG=H VG: Externally applied, HP Mode No-load operating, MCK=256fs, DIN1,DIN2=16fs,ENREG=H VG=5V MCK, DIN1, DIN2 BEEPIN, MODEB EN1, EN2, ENREG, ENVG MCK, DIN1, DIN2 BEEPIN, MODEB EN1, EN2, ENREG, ENVG 4.0 7.7 7.7 -50 (2.45) -41 (6.91) 2.0 5.0 1.2 1.2 11 11 -48 (3.08) -39 (8.70) 2.6 5.75 2 2 14.3 14.3 -46 (3.88) -37 (10.95) 1 V V PARAMETER VDD Supply Voltage VG Supply Voltage HP Driver High side Resistance HP Driver Low side Resistance Line Driver High side Resistance Line Driver Low side Resistance BEEP Output Voltage SYMBOL VDD VG RHPH RHPL RLINEH RLINEL VBEEPL VBEEPH dBm (mVrms) Power Supply Current At Standby IST A IDD1 Power Supply Current At Operating (Mute signal input) IREG1 IDD2 IREG2 IG2 VIH Digital Input Voltage VIL Input Leakage Current Pull-down Resistance ILK RPD 0.7VDD 0 150 0.95 0.70 0.05 0.70 0.75 300 1.6 mA 1.2 0.10 1.2 1.2 VDD 0.3VDD 1 450 V V A k mA Ver.2005-03-09 -7- NJU8715 (2) REGULATOR CHARACTERISTICS (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) CONDITIONS MIN TYP MAX UNIT HP MODE LINE MODE HP MODE VCONT=1.5V, VREG=2.5V HP MODE VCONT=0.5V, VREG=2.5V LINE MODE VCONT=1.5V, VREG=3.5V LINE MODE VCONT=0.5V, VREG=3.5V 1.9 3.0 1.9 0.23 2.8 0.38 70 60 Iout=70mA VDDO1, 2=1.7V Vr=0.1Vrms, Iout=70mA fr=1kHz IREGO=0 ~ 24.3mArms VCONT=0.1V 36 0 2.15 2.0 0.33 2.9 0.48 44 4.0 4.0 2.1 0.43 3.0 0.58 0.2 520 10 VREG V V V V V V mA mA V dB Vrms PARAMETER Input Voltage SYMBOL VREGH VREGL VDDOH1 Output Voltage VDDOH2 VDDOL1 VDDOL2 Output Current Sink Current Dropout Voltage Ripple Rejection Load Regulation Voltage Residual Voltage VCONT IOUT ISINK VIO RR VLR VMIN VCONT mV V The following figure shows a representative example of VCONT versus VREGO. At VCONT=1.5V: VREGO=2.0V(VREG=2.5V) in HP MODE, VREGO=2.9V(VREG=3.5V) in LINE MODE. At VCONT=0.5V: VREGO=0.33V(VREG=2.5V) in HP MODE, VREGO=0.48V(VREG=3.5V) in LINE MODE. 4.0 3.5 3.0 VREGO (V) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VCONT (V) LINE MODE HP MODE -8-8- Ver.2005-03-09 NJU8715 NJU3555 (3) AC CHARACTERISTICS Master Clock PARAMETER Frequency Pulse Width (H) Pulse Width (L) (Ta=25C, VDD=2.0V, VDDO1=VDDO2=1.7V, VREG=2.15V, VSS=VSSO=0.0V, Load Impedance=16, fS=44.1kHz, unless otherwise noted) SYMBOL fMCKI tMCKH tMCKL CONDITIONS MIN 8 8 8 TYP MAX 50 UNIT MHz ns ns * * Digital Audio Data PARAMETER DIN1, DIN2 Setup Time DIN1, DIN2 Hold Time EN1, EN2, ENREG, ENVG, BEEPIN, MODEB Rise Time, Fall Time SYMBOL tDS tDH tEr, tEf CONDITIONS MIN 5 5 - TYP - MAX 50 UNIT ns ns ns tMCKH MCK tMCKL 0.7VDD 0.3VDD tDS tDH 0.7VDD 0.3VDD DIN1, DIN2 MCK, DIN1, DIN2 Timing chart 0.7VDD 0.3VDD tEr tEf EN1, EN2, ENREG, ENVG, BEEPIN, MODEB Timing chart Ver.2005-03-09 -9- NJU8715 APPLICATION CIRCUIT (1) Using Internal VG (ENVG=H) MCK DIN1 DIN2 BEEPIN 10F 2.2F OBEEP1 47H 0.22F 220F 4.7k OUT1 Regulator Input VREG 16 Head Phone VSS VSS OBEEP2 47H 0.22F 220F 4.7k CFB VREGO 220F VDDO1 1F NJU8715 OUT2 16 Head Phone 1F VDDO2 VCONT VREF VREGO Control Signal 10F CH 0.1F MODEB CL VG 1F VDD 2.2F VDD 100F ENREG ENVG EN1 EN2 VSS - 10 - 10 - Ver.2005-03-09 NJU8715 NJU3555 (2) VG: Externally applied (ENVG=L) MCK DIN1 DIN2 OBEEP1 47H 220F 4.7k OUT1 0.22F 10F 2.2F Regulator Input BEEPIN VREG 16 Head Phone VSS VSS OBEEP2 47H 0.22F 220F 4.7k CFB VREGO 220F VDDO1 1F NJU8715 OUT2 16 Head Phone 1F VDDO2 VCONT VREF VREGO Control Signal 10F CH MODEB CL ENVG EN1 EN2 VDD 2.2F VDD 100F VG 1F ENREG VG VSS Note.7) CH and CL pins must be opened when VG externally applied. Note.8) De-coupling capacitors must be connected between each power supply pin and GND pin. The capacitor value should be adjusted on the application circuit and the temperature. It may malfunction if capacity value is small. Note.9) A large-capacitance for the de-coupling capacitors for headphone speaker is recommended to improve a low-frequency characteristics. In addition, a low-ESR(Equivalent series resistance) capacitor is recommened for high power efficiency. Note.10) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2005-03-09 - 11 - |
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